[hpsdr] Ozy and the new code release

[Kirk Weedman]

I would like to gather some information on the new FPGA code release.  
LED D1 flashes a code under certain conditions.  If D1 is flashing 
please send me the code which I will explain below, which version of 
FPGA (C8 or C7), which boards are installed, and whether you have any 
audio or other problems.  This may help me determine some issues in the 
design.  I would like this info from people that ARE having problems and 
people that ARE NOT apparently having problems.

Code:  D1 flashes a 4 bit value.  Least significant bit is flashed first

Here's what a value of 0 looks like
            +---+           +---+           +---+           +---+
D1 ---------+   +-----------+   +-----------+   +-----------+   
+-----------+------------------------
                0 (LSB)             0               0               
0         dead time between 4 bit flashes
Here's what a value of 4 looks like

            +---+           +---+           +----------+    +---+
D1 ---------+   +-----------+   +-----------+          +----+   
+-----------+---------------------
                0                  0                1               0

More details can be seen near the bottom of the ozy_janus.v code if 
interested.

Thanks
Kirk KD7IRS