[hpsdr] FPGA Speed Grade on Ozy

[Scott Cowling]

OK, here's the real story dug up from the paper archives.

Due to our supplier's inability to deliver enough Altera FPGAs in 
time for us to complete the Ozy build prior to Dayton in 2007, we 
purchased FPGAs from three different vendors.

162 of them were C7 speed grade
495 of them were C8 speed grade

Notice that the total is 657 even though we built only 650 boards. 
This allows a couple of spares.

So, up to 162 boards out there in HPSDR-land have the faster chip on 
them. Before you get to thinking that your board is better because 
you have the faster chip (or worse due to the slower chip), here are 
some figures for you from the Altera Cyclone II handbook regarding performance:

16-bit counter, f(max)
C8:  310.65MHz
C7:  349.4MHz

18x18 multiplier, f(max)
C8:  180.57MHz
C7:  216.73MHz

8-bit, 16-tap FIR filter, f(max)
C8:  110.57MHz
C7:  131.25MHz

Maybe Kirk can comment, but I don't think we are anywhere close to 
the f(max) limits on anything we do in Ozy. Of course, that does not 
mean that there isn't a bug that a faster FPGA "fixes".

Just like putting 667MHz SDRAM on your PC bus that runs at 533MHz, a 
faster FPGA does not run any "faster" just because it is a C7 instead 
of a C8. It only has to be "fast enough" to keep up with the clock 
given the internal logic that is programmed into it.

It would be informative to see if anyone has a C7 FPGA that exhibits the bug.

Also note that FPGAs run marginally slower when they are hot. If the 
problem is right on the edge, that might explain why the boards work 
for a while and then degrade after they heat up.

Welcome to the "fun" world of FPGA debug! Hope this is somewhat helpful.

73,
Scotty WA2DFI



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