[hpsdr] OZY & new code release

[K1rqg at aol.com]

My observations with latest code: 
 
OZY C8N  D1 is not flashing when software is running.
Receive audio appears to be fine at all three sample rates.
Transmit audio exhibits distortion when viewed on another SDR or a Spectrum 
 analyzer
    it is worse at 96000 sample rate, but still visible at  192k and 48k. 
You cannot rely on
    "on the air" reports from all stations. It is not always  acknowledge 
by most stations
    using analog radio. 
 
 
OZY C7N  D1 is not flashing when software is running.
Receive audio appears to be fine at all three sample rates.
Transmit audio exhibits distortion when viewed on another SDR or a Spectrum 
 analyzer
    it is worse at 96000 sample rate, but still visible at  192k and 48k. 
You cannot rely on
    "on the air" reports from all stations. It is not always  acknowledge 
by most stations
    using analog radio. 
 
As can be seen from above, in RECEIVE mode, all is well with latest  code 
and both C8N & C7N OZY.
I have one of the C8N OZY boards that was a problem with OZY 13 with relay  
chatter and distorted
receive audio. OZY 14 fixes the receive issues but has introduced a  
transmit issue. Again, listening
to the HPSDR on analog radio does not necessarily exhibit "bad" audio, but  
when monitored by
another "reliable" SDR radio (and spectrum analyzer), the waveform tells  
all. BTW, I tried two 
Penelope boards and two Mercury boards as well.
 
Has anyone else checked their transmit signal? K5SO & I checked each  other 
and were able
to see on the air what I have described above. Reverting back to May 29  
code cleared the 
transmit problem.
 
 
73 de Joe
K1RQG


 
 
In a message dated 6/14/2009 2:36:51 P.M. Eastern Daylight Time,  
kirk at hdlexpress.com writes:

*****  High Performance Software Defined Radio Discussion List *****

I would  like to gather some information on the new FPGA code release.  
LED D1  flashes a code under certain conditions.  If D1 is flashing 
please  send me the code which I will explain below, which version of 
FPGA (C8 or  C7), which boards are installed, and whether you have any 
audio or other  problems.  This may help me determine some issues in the  
design.  I would like this info from people that ARE having problems  and 
people that ARE NOT apparently having problems.

Code:  D1  flashes a 4 bit value.  Least significant bit is flashed  first

Here's what a value of 0 looks like
+---+           +---+   +---+         +---+          
D1  ---------+   +-----------+   +-----------+    +-----------+    
+-----------+-----------------------------------
0 (LSB)         0                0               0       dead time between 
4 bit flashes
Here's what a  value of 4 looks like

+---+           +---+         +----------+    +---+           
D1 ---------+   +-----------+   +-----------+   +----+    
+-----------+-----------------------------------
0           0               1               0

More  details can be seen near the bottom of the ozy_janus.v code if  
interested.

Thanks
Kirk  KD7IRS




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