[hpsdr] Diversity reception w/dual Merc boards

[Joe Martin K5SO]

Hi Georg,

Nope, as Kirk noted.  The ADCs on the two boards are not  
synchronized.  The synchronization I was referring to has to do with  
how Ozy inserts the serial data stream from the second Mercury into  
the combined data stream to the USB port.  The problem with the Ozy  
code was that it would randomly start inserting the second stream in  
the middle (or elsewhere) of the byte stream of an ADC conversion  
value, not at the beginning of the value.

I don't believe there is an input pin on the ADC chips to allow one to  
do that easily.  However, as Phil suggested to me, by using the A19  
Atlas bus line to provide a reset signal it is easy to apply a general  
reset to both boards simultaneously, including resetting their  
CORDICs, decimation routines, and other logic elements in the FPGAs so  
that they both are restarted at the same instant and, since they run  
on the same clocks, they can be "pseudo-synchronized" in that way.

Recently I have used the A19 line to generate such a reset to both  
FPGAs but I didn't find that it made any noticeable difference here  
relative to phasing...but in truth I didn't look carefully at it at  
the time.

Currently, the two Mercury boards run "independently" generating two  
relatively independent streams of serial data, but they are using the  
same clocks, of course.  The two streams are combined into one single  
interleaved stream in the Ozy FPGA  and then passed to the USB port.   
Even with this non-locked scheme the practical relationship  between  
the two streams is such that the phases of the two IQ byte streams  
allows simple combining in the PC without any apparent distortion.   
One could look carefully at it and obtain a measurement of how well  
they are synchronized.

73,  Joe K5SO

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