[hpsdr] [ATLAS] Alpha bare board pictures posted - April 6, 2006

[Ray Anderson]

On 4/6/06, vk4str <vk4str at netspace.net.au> wrote:
>> Hi Phil and group,
>>
>> The photos of Atlas are looking really good, congrats Phil!
>>
>> Makes me feel like wanting to heat up the soldering iron, hi! No
doubt
>> you will be doing that right now.
>>
>> I do have one comment regarding the Atlas concerning the bypass
>> capacitors near the ATX PS connector. Due to the length and width of
the
>> connecting tracks from the ATX pads the bypass C's wont be very
>> effective. IMHO it would be better and more effective if they were
moved
>> as close as possible to the ATX pads with the shortest possible track
>> length and maximum track width.
>>
>> Alternatively another solution would be to have a GND area
sourrounding
>> the ATX connector on the bottom layer with enough Vias to the top GND
>> for low impedance, and to position the bypass C's on the bottom layer
>> very close to the actual ATX connector pads.
>>
>> Or a mixture of the above, bypass C's mounted on top and bottom to
>> maximize effectiveness by minimizing connecting track lengths.
>>
>> I had a look at the FPGA-USB board schematic, WOW!! Phil you really
have
>> got the Adrenalin flowing! This is an absolutely outstanding effort
>> Phil. I need to have a look at the block diagram if I can find it, to
>> better understand the connectivity within system components. This is
>> exactly what I have been thinking of for a long time.
>>
>> Thanks for the great efforts.
>>
>> 73, Helmut VK4STR

>Hi Helmut,

>There is certainly nothing to stop people from adding some more bypass
>caps on the underside of the board if they find that they need them. 
>The ground pins on the ATX connector are close enough and distibuted
>enough to allow the placement of some 0805 ceramics right at the power
>pins.

>73 de Phil N8VB
_


Helmut-

Another thing to consider is that C1 thru C5 (the 10uF parts near the
ATX connector) which will have quite a bit higher mounted inductance
than most of the smaller decaps in the design (due to the longer escape
trace) will have a much lower self resonant frequency due the larger
capacitance. These parts will be most effective up to around a MHz. They
will also have a rather broad resonance. So a little extra mounting
inductance won't turn out to be a real killer. The lower the SRF, the
more liberties you can take with the mounting inductance.

Also, consider that there are no active parts on the ATLAS board. The
real critical bypassing will be on the application boards (Mercury,
Lionheart, Janus, etc. ....) where the active current consuming parts
will reside. The bypassing on ATLAS is intended to provide reasonable
low impedance between the power busses and gnd. Since there won't be any
terribly fast risetime signals or current consumers on ATLAS the target
impedance can afford to be pretty high without much effect on the
function of the system.

This is also an alpha design. Once we get some functioning boards
plugged into the backplane and if we determine there are any PDN issue
associated with ATLAS (which we really don't expect) the decoupling can
be modified at that point. If proved to be necessary, improved bypassing
could most easily be provided on these parts by leaving them exactly
where they are and dropping vias  directly to the power planes on layer
3 with short escape traces to the decap pads on layer 1. 

You comments on the proper placement of the capacitors are absolutely
correct if you need to provide a very low broadband impedance on an
active board, however in the case of the ATLAS this isn't the driving
factor.

73's,  Ray   WB6TPU
Santa Cruz, CA



Raymond Anderson
Senior Signal Integrity Staff Engineer
Product Technology Department
Advanced Package R&D
Xilinx Inc.

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