[hpsdr] Janus Update

[pvharman at arach.net.au]

Been a little behind updating the group on the work Bill and I are doing on 
the Janus board. 

I now have a Cirrus Logic CS5381 A/D chip along side the TI PCM4202 and 
Wolfson WM8785 for testing.

I’m having a problem testing the Cirrus chip in that there are some low level 
close in spurs near the 0Hz point that I can’t account for.  Even so the noise 
floor of the Cirrus is some 6dB below the PCM4202. 

The Cirrus also needs an external input conditioning circuit and this has 
given me a few problems.  Unlike the other two A/D chips the Cirrus has a 
relatively low input impedance and the first opamp input circuit I built did 
not like driving it.  Using a different opamp solved that problem but the 
replacement does not like the 2700pf across its output that the CL evaluation 
circuit shows.

So I’ve decided to build exactly the circuit that CL  show in their 
application note AN241 using the opamps they specify. The opamps are on their 
way and should be here next week.

On the software side Bill is working on taking the  2 x 24 bit 48kHz  signal 
inputs and 1 x 16bit 48kHz microphone input over the USB and processing them 
in PowerSDR.  These will be processed by PowerSDR and sent out over the USB to 
provide the  L/R audio outputs at headphone level from the TLV320AIC23B and  
I/Q signals from the FPGA PWM  D/A converters.  The fact that Bill found a bug 
in the PowerSDR code that had the block size locked at 2048 hindered progress 
for a while but with that resolved he is making good progress.

We will do bake-offs of the three A/D converters at 48 and 96kHz and based on 
the results make a final selection. 

Apart from the A/D I have most of the remaining Janus circuit diagram drawn in 
Kicad.

73's Phil...VK6APH 


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