[hpsdr] Janus Lives!!

[Eric Ellison]

HI Phil!

TRULY ASTOUNDING! A big THANKS to all! I didn't know it could go that low!

Now if we can find about 400 AKI chips! (smile).

Eric

-----Original Message-----
From: hpsdr-bounces at hpsdr.org [mailto:hpsdr-bounces at hpsdr.org] On Behalf Of
Phil Harman
Sent: Monday, July 03, 2006 8:45 AM
To: High Performance Software Defined Radio Discussion List
Subject: [hpsdr] Janus Lives!!

***** High Performance Software Defined Radio Discussion List *****

All,

I've just completed the CPLD software for the Alpha Janus board and the 
results are spectacular.

The image below is of the Janus sampling at 48kHz.  As you can see the noise

floor is at a spectacular -159dBm (it actually hovers around -160dBm but 
that is when I captured the screen). As you can see there are absolutly no 
spurs in the passband.

The file name is "Janus noise floor.jpg"  for those that have a problem with

getting files from www.hamsdr.com

http://www.hamsdr.com/personaldirectory.aspx?id=348

The second screen shot is at 48kHz in spectrum mode. Again no spurs and the 
signal at 0Hz is -120dBm. This drops below the band noise when I connect the

SDR1000 hardware.

http://www.hamsdr.com/personaldirectory.aspx?id=349

The file name is "Janus spectrum.jpg"

I still have some more tests to do as well as testing  at 96/192kHz but so 
far all is looking great.

There are a small number of minor changes to the prototype PCB which will be

addressed shortly.  My sincere thanks to Lyle KK7P for doing such a great 
job on the PCB design, Bill KD5TFD for the PowerSDR software modifictions so

Janus will work with it and help with the Verilog coding and all those who 
helped me up the FPGA learning curve.

Onwards to OZY!!

73's Phil...VK6APH








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