[hpsdr] Testing the Boards

[Bill Tracey]

Hi Bruce -- I think most of us bringing this stuff up are trying to write 
up the gotcha's we see and the little test tools.  I've done test images 
for the FPGA on Ozy and the CPLD on Janus and they are in SVN.   They 
simply take a clock in on one pin and divide it down and put different 
freqs on the output pins.  Makes it simple to validate the chip is 
correctly soldered by running around with a scope.

I also know Phil C's got some Ozy test routines in SVN as well.

We're also trying to keep decent builders notes and needed changes lists on 
the wiki - so far that seems to be going pretty good.

Cheers,

Bill




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