[hpsdr] [CASMIR] Design v0.3

[Alex]

Ok, I've posted a draft design at (http://www.hamsdr.com/personaldirectory.aspx?id=285), updated with Wiki with a link.
The drawing is in the same format as the visio file for the other boards.

There are three directions the design can go:

(1) Use the AD9958 and generate the LO from the FPGA
(2) Use a AD9959 and don't let the FPGA generate the LO
(3) eliminate the DDS and let the FPGA do all the work 

Any thoughts?

CASMIR is dependant on new Reflock VHDL code from GIBRALTAR.
CASMIR is reusing the basic circuit configuration from JANUS (ATLAS bus to FPGA).

Alex, N3NP