[hpsdr] "Taylor Corrected DDS"
Bob McGwier
n4hy at idaccr.org
Wed Jun 14 11:04:34 PDT 2006
This is really straightforward and was what we used for the sinusoidal
oscillator back in the visual basic code for the SDR-1000 in our
numerically controlled oscillator before we figured out how fast modern
desktop/laptop CPU's are when doing floating point arithmetic. In
fact, we did not need it at all for our PC based NCO's. But in FPGA and
DDS's, it is a boost and this set of tricks should be filed away in
your repertoire even if ultimately they do not prove useful here.
It is based upon nothing more sophisticated than sin(a+b) and cos(a+b)
and trigonometric identities.
The "Taylor corrected" is all marketing hype. You are making a first
order correction to the sinusoid from a table lookup and that means you
have done a first order Taylor series expansion that amount to nothing
more than linear interpolation where the interpolating steps are
quantized. It sounds very sexy. It is not.
That said, this will be a really great experiment for us to conduct
with our ALTERA parts (to shove it to Xilinx for doing this kind of hype).
sin(a+b) = sin(a)cos(b) + cos(a)sin(b)
and
cos(a+b) = cos(a)cos(b) - sin(a)sin(b)
And the magic is over ;-).
There has never been a simpler problem that is more illustrative of WHY
one should think of these things as complex numbers. These same two
identities are one trivial identity in complex numbers.
exp(j (a+b)) = exp(ja)exp(jb) (because the arguments are exponents)
is the entire thing (if you follow Euler's identity in its exp(j C)
= cos(C) + j sin(C) you will see it immediately).
So let us suppose that we wish to have 4096 points in our main look up
table. This is 2^12 points so we are looking at 12 bits of our
accumulator for A. There is NO advantage in our procedure for doing
more than just truncating the phase Phi to 12 bits and calling the
truncation a, an integer.
The residual phase error not taken into account by our truncated phase
is Phi - a. Notice since we truncated Phi to twelve bits, Phi - a
is ALWAYS nonnegative. This is a definite plus. Let us add a new table
of complex numbers 256 long and it will be
exp(j b) where b takes on the values
b = 2 * i * pi /(256*4096) where i can take on the values 0,1,
..., 255. Pick the i from 0 - 256 so that Phi - a -
(2*i*pi/(256*4096))is MINIMIZED. If i is 256, add one phase step to
a and make b = 0. Otherwise, b is in our little 256 long table of
complex numbers.
The final complex sinusoid output is exp(ja)exp(jb) and we have
tremendously reduced the total harmonic distortion and phase truncation
spurs. But all we have is two table lookups. In simple terms, you
have broken up the phase circle in 256*4096 or 2^20 pieces BUT, using
the trig identities above we can do the entire 2^20 different points
with a single 2^12 lookup and a 2^8 lookup. So in two table lookups,
you get a very nice complex number with much lower phase truncation crud
than the 2^12 lookup.
So, what is the catch? They have NOT told to you in the dds paper
from Xilinx how to make the analog signals, the voltages for the RF
combine for the final output. Notice that the entire block diagram set
ends in the table lookups. The hard part is what must then follow. For
the real channel we need
cos(a)cos(b) - sin(a)sin(b) for example. This is a summer and two
mixers running at RF frequencies and we expect them to be perfectly
balanced, etc. We need to figure out how to do the two multiplies and a
subtract to take advantage of the trivial trig identities and we need to
do a pair of these, again perfectly balanced and identical group delay
to produce signals in quadrature. Running at tens to hundreds of MHz,
this is a nontrivial issue. Analog devices has spent tons of money
learning how to make these nonlinear processes produce linear results.
We do not have this at our disposal. We are better off spending a few
tens of dollars to get a DDS and feeding it to a PLL if you want spur
free (and phase noise increased) operation.
Bob
N4HY
--
Robert W. McGwier, Ph.D.
805 Bunn Drive
Princeton, NJ 08540
(609)-924-4600
(sig required by employer)
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