[hpsdr] CASMIR LO Design

[Alex]

Unless there are any objections, I suggest we go with a UR3IQO-derived LO design.  

We would investigate constructing a frequency synthesizer with a multiplication factor of 1 that UR3IQO discusses on p33 of the article. He states that with a low-noise reference oscillator (in our case a GPS-disciplined reference oscillator - GIBRALTAR), a highly linear PFD and wide loop bandwidth, one could get "very good" VCO noise suppression. Then end result being a "super synthesizer". The "Taylor corrected" discussion and maths with N4HY should be considered for inclusion.

Plus we should implement on an Altera FPGA to keep consistent with the rest of the design.

Any volunteers to help with implementing the VHDL?

Alex, N3NP