[hpsdr] [CASMIR] Design v0.3

[Alex]

Chris,
A little too much cut-n-pasting and not enough editing on the airplane. I put the ADL5390 in place of the AD8345/AD8349 modulators for the drawing. The AD8345/AD8349 is used by the USRP, but I was looking at the ADL5390 as an alternative. 



This leads to my query to everyone on LO and I/Q generation. I need some solid arguments not some "I used DDSes in the past and they suck.", but some good technical discussions. So ... here are three directions the design can go:

(1) Use the AD9958 and generate the LO and the DDS reference clock from the FPGA
(2) Use a AD9959 and don't let the FPGA generate the LO, just the reference clock for the DDS
(3) eliminate the DDS and let the FPGA do all the work 

It's an open design, I'm putting it on the table and looking for lots of useful input. OR add your own option.

Alex, N3NP

----- Original Message ----
From: Christopher T. Day <CTDay at lbl.gov>
To: Alex <harvilchuck at yahoo.com>; hpsdr at hpsdr.org
Sent: Tuesday, June 6, 2006 7:25:22 PM
Subject: RE: [hpsdr] [CASMIR] Design v0.3

Alex,

I'm a little confused by your design sheet. It says that Casmir is based
on the AD834X family of modulators, but the block diagram doesn't
include one. Am I missing something? Thanks.


    Chris - AE6VK


-----Original Message-----
From: Alex [mailto:harvilchuck at yahoo.com] 
Sent: Monday, June 05, 2006 6:39 AM
To: hpsdr at hpsdr.org
Subject: [hpsdr] [CASMIR] Design v0.3

***** High Performance Software Defined Radio Discussion List *****

Ok, I've posted a draft design at
(http://www.hamsdr.com/personaldirectory.aspx?id=285), updated with Wiki
with a link.
The drawing is in the same format as the visio file for the other
boards.

There are three directions the design can go:

(1) Use the AD9958 and generate the LO from the FPGA
(2) Use a AD9959 and don't let the FPGA generate the LO
(3) eliminate the DDS and let the FPGA do all the work 

Any thoughts?

CASMIR is dependant on new Reflock VHDL code from GIBRALTAR.
CASMIR is reusing the basic circuit configuration from JANUS (ATLAS bus
to FPGA).

Alex, N3NP
 


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