[hpsdr] [CASMIR] Design v0.3

[Phil Harman]

Not sure I agree about the use of an FPGA to do the NCO.  I've been using 
the free Altera NCO Megafunction to design the  complex oscillator so we can 
test the LT2208.

With an FPGA there are a lot of design parameters you can change and see the 
effect on the level of spurious signals with the Altera design software.  By 
using lots of phase and amplitude bits you can get a very clean DDS. I guess 
that will be degraded when we have to add a DAC to get into the real world 
for a transmitter. Even so it looks like a viable option and one we will be 
using in the Mercury board.

For HF I would be very interested in looking at a microwave VCO ( say 3GHz) 
driving a series of dividers to reduce the phase noise.  A number of 
commercial radios do this as well as the TT Orion I believe. We only need 
about 10kHz steps at HF since we can interpolate in software.  I know that 
Chris Bartram is an expert in factional N freq synths so expect that is the 
way that the uWSDR group will go.

Alex, how do you intend to provide Tx signals from 1 - 10MHz since I see the 
lower frequency of the AD chip you propose to use is 10MHz?

I think that it is important that we use complex mixers where we can trim 
the amplitude and phase values to optimise sideband suppression. Otherwise 
40dB of attenuation is not going to win you any friends with the locals on 
2m, especially if your unwanted sideband is 10s kHz  away from your main 
signal.

73's Phil....VK6APH






----- Original Message ----- 
From: "David Bengtson" <davemailinglist at verizon.net>
To: "Alex" <harvilchuck at yahoo.com>
Cc: <hpsdr at hpsdr.org>
Sent: Wednesday, June 07, 2006 6:18 PM
Subject: Re: [hpsdr] [CASMIR] Design v0.3


> ***** High Performance Software Defined Radio Discussion List *****
>
> Alex wrote:
>> ***** High Performance Software Defined Radio Discussion List *****
>>
>> Ok, I've posted a draft design at 
>> (http://www.hamsdr.com/personaldirectory.aspx?id=285), updated with Wiki 
>> with a link.
>> The drawing is in the same format as the visio file for the other boards.
>>
>> There are three directions the design can go:
>>
>> (1) Use the AD9958 and generate the LO from the FPGA
>> (2) Use a AD9959 and don't let the FPGA generate the LO
>> (3) eliminate the DDS and let the FPGA do all the work
>>
>> Any thoughts?
>>
>> CASMIR is dependant on new Reflock VHDL code from GIBRALTAR.
>> CASMIR is reusing the basic circuit configuration from JANUS (ATLAS bus 
>> to FPGA).
>>
>> Alex, N3NP
>
> I'm of the opinion that using an FPGA to generate a reference signal is
> a bad idea from a spurious/noise point of view. I haven't looked at the
> AD data sheets in a long time, but I'd be inclined to recommend option
> 4, use a real crystal oscillator to generate the LO for the DDS.
>
>
> Dave
>
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