[hpsdr] Mercury

[John B. Stephensen]

Yes, it will be placed on the ARRL web site.

73,

John
KD6OZH

----- Original Message ----- 
From: "Christopher T. Day" <CTDay at lbl.gov>
To: "John B. Stephensen" <kd6ozh at comcast.net>; "Philip Covington"
<p.covington at gmail.com>
Cc: <hpsdr at hpsdr.org>
Sent: Sunday, June 11, 2006 06:05 UTC
Subject: RE: [hpsdr] Mercury


John,

Will the Verilog be available for study once the article is published?
Sounds fascinating.


Chris - AE6VK


-----Original Message-----
From: John B. Stephensen [mailto:kd6ozh at comcast.net]
Sent: Saturday, June 10, 2006 8:00 PM
To: Philip Covington
Cc: hpsdr at hpsdr.org
Subject: Re: [hpsdr] Mercury

***** High Performance Software Defined Radio Discussion List *****

It would be nice to have at least as many resources as a Xilinx XC3S400
(16
18k dual-port RAMs, 16 18x18 multipliers and 7200 logic elements). I'm
finishing off the second implementation of an OFDM modem on the XC3S400
and
it would be nice to have more hardware available for it to run on. The
modem
is being done as an ARRL HSMM WG project and I'm planning on publishng
the
design in QEX. Fast VHF and UHF modems should be of interest to TAPR
members.

Also, consider the Xilinx XC3S500E. Its very inexpensive, available in a
QFP, and has 20 18k RAMs, 20 multpliers and  9,300 logic elements. The
free
Xilinx development tools now include the Core Generator which contains
free
CORDIC and FFT implementations in addition to simpler functions.

The OFDM modem is much more resource-efficient than my first
implementation
and is designed for run-time configurable carrier spacing and bandwidths
so
that 64 to 1,8432 kbps data rates can be supported. The implementation
is in
Verilog and includes a DDC, interpolating/decimating FIR low-pass
filters,
FFT (Xilinx), phase modulator, phase demodulator (Xilinx CORDIC),
convolutional encoder and Viterbi decoder. It is meant to be used with a
12.288 Msps ADC and a 6.144 Msps dual DAC. The low sampling rates allow
the
DDC, filters and Viterbi decoder to be much smaller than the Xilinx IP.
With
an FPGA like the XC3S500E, a much higher sampling rate could be
supported.

73,

John
KD6OZH

----- Original Message ----- 
From: "Philip Covington" <p.covington at gmail.com>
To: "John B. Stephensen" <kd6ozh at comcast.net>
Cc: <hpsdr at hpsdr.org>
Sent: Saturday, June 10, 2006 01:04 UTC
Subject: Re: [hpsdr] Mercury


> On 6/9/06, John B. Stephensen <kd6ozh at comcast.net> wrote:
> > ***** High Performance Software Defined Radio Discussion List *****
> >
> > What size FPGA is planned for the Mercury board?
> >
> > 73,
> >
> > John
> > KD6OZH
>
> Hi John,
>
> Phil H and I were just talking about this.  It is TBD...but I can say
> it won't be the little Cyclone II on the OZY.  We should have a better
> idea pretty soon.  I was doing some filter design stuff with MATLAB
> today.  I want it to be big enough to be able to do some serious DSP
> in it.
>
> 73 de Phil N8VB

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