[hpsdr] Mercury

[John B. Stephensen]

I'd like to limit distribution to the version that supports VHF as I have
learned quite a bit about efficient use of Xilinx FPGAs during the project.
I could make files available in July or August after I've done some testing
on 6 meters and submitted the article. I do use the Xilinx core generator
for some functions so its not directy compilable for other FPGAs.

73,

John
KD6OZH

----- Original Message ----- 
From: "Eric Blossom" <eb at comsec.com>
To: "Christopher T. Day" <CTDay at lbl.gov>
Cc: "John B. Stephensen" <kd6ozh at comcast.net>; "Philip Covington"
<p.covington at gmail.com>; <hpsdr at hpsdr.org>
Sent: Sunday, June 11, 2006 14:23 UTC
Subject: Re: [hpsdr] Mercury


> On Sat, Jun 10, 2006 at 11:05:17PM -0700, Christopher T. Day wrote:
> > ***** High Performance Software Defined Radio Discussion List *****
> >
> > John,
> >
> > Will the Verilog be available for study once the article is published?
> > Sounds fascinating.
> >
> > Chris - AE6VK
>
> Why wait for the article ;)
>
> Is the code available now?  Perhaps in CVS or SVN?
>
> Eric
>
>
> > -----Original Message-----
> > From: John B. Stephensen [mailto:kd6ozh at comcast.net]
> > Sent: Saturday, June 10, 2006 8:00 PM
> > To: Philip Covington
> > Cc: hpsdr at hpsdr.org
> > Subject: Re: [hpsdr] Mercury
> >
> > ***** High Performance Software Defined Radio Discussion List *****
> >
> > It would be nice to have at least as many resources as a Xilinx
> > XC3S400 (16 18k dual-port RAMs, 16 18x18 multipliers and 7200 logic
> > elements). I'm finishing off the second implementation of an OFDM
> > modem on the XC3S400 and it would be nice to have more hardware
> > available for it to run on. The modem is being done as an ARRL HSMM
> > WG project and I'm planning on publishng the design in QEX. Fast VHF
> > and UHF modems should be of interest to TAPR members.
> >
> > Also, consider the Xilinx XC3S500E. Its very inexpensive, available
> > in a QFP, and has 20 18k RAMs, 20 multpliers and 9,300 logic
> > elements. The free Xilinx development tools now include the Core
> > Generator which contains free CORDIC and FFT implementations in
> > addition to simpler functions.
> >
> > The OFDM modem is much more resource-efficient than my first
> > implementation and is designed for run-time configurable carrier
> > spacing and bandwidths so that 64 to 1,8432 kbps data rates can be
> > supported. The implementation is in Verilog and includes a DDC,
> > interpolating/decimating FIR low-pass filters, FFT (Xilinx), phase
> > modulator, phase demodulator (Xilinx CORDIC), convolutional encoder
> > and Viterbi decoder. It is meant to be used with a 12.288 Msps ADC
> > and a 6.144 Msps dual DAC. The low sampling rates allow the DDC,
> > filters and Viterbi decoder to be much smaller than the Xilinx IP.
> > With an FPGA like the XC3S500E, a much higher sampling rate could be
> > supported.
> >
> > 73,
> >
> > John
> > KD6OZH
>


 1150053234.0