[hpsdr] More Mercury

[Philip Covington]

On 6/12/06, Phil Harman <pvharman at arach.net.au> wrote:
> I've been able to interface the LT2208 demo board to the Xylo and hence to
> PowerSDR. The screen shot at
>
> http://www.hamsdr.com/dnld.aspx?id=328
>
> show a +10dBm signal at 25MHz directly into the LT2208.  With the image
> amplitude and phase controls at 0 and 0 respectively there is no visible
> image.
>
> The FPGA interface to the LT2208 is very crude at the moment. I've using a
> fixed NCO at 25MHz followed by a CIC filter decimating by 2048 since this
> gives ~48kHz from the 100MHz clock. You can see the sinx/x shape of the
> noise floor, the CIC needs following with a compensating FIR to flatten
> this.
>
> The CIC is also very simple, this is the design file from MatLab
>
> // Discrete-Time FIR Multirate Filter (real)
> // -----------------------------------------
> // Filter Structure        : Cascaded Integrator-Comb Decimator
> // Decimation Factor       : 2048
> // Differential Delay      : 1
> // Number of Sections      : 3
>
> I've chosen the input frequency on the screen shot to get rid of all of the
> spurs - there are still lots of them but I guess a better CIC and FIR will
> clean a lot of them up.  The bandscope vertical scale is wrong since I am
> sending 16 bits from the LT2208 and PowerSDR is expecting 24. Still it
> lools like we are getting the full 16 bits from the LT2208 since you can see
> about 96dB of DR.  What is intersting is that with no signal input the
> output from the LT2208 is 0, the LSB never moves, so the internal noise
> looks very good.
>
> We are going to need a decent pre-amp for the high bands but even so the
> initial results look quite good.
>
> Must sleep!!
>
> 73's Phil...VK6APH

Hi Phil,

Looks great.  Yep, the passband slope of the CIC is pretty evident.

I wonder what effect you see when you enable the dithering on the eval
board?  It would be interesting to see if it makes any difference.

The oscillator I sent with the eval board is a Cystek true sinewave
model.  The data sheet is at:

<http://www.crystek.com/spec-sheets/CCO-083_085.pdf>

Since the LTC2208 can deal with a sinewave encode clock, I figured
that this model was a good one to start with.  It is kind of
expensive, somewhere around $40.

The one thing I was concerned about is that Linear recommends up to
+3dBm (as I recall) input level for a sinewave encode clock and I
think the Crystek is 0dBm.  There are options in that particular part
for higher level outputs, but they are special order.

Here is another crystal oscillator that I ordered to try:

<http://www.crystek.com/spec-sheets/vcxo/CVHD-950.pdf>

The quality of the encode clock will be really important for
undersampling applications.

I will send an email off the Linear Technology's app engineer for the
high speed ADC stuff and ask for a recommendation for the encode
clock.

I should have the cordic based NCO verilog code ready to send you by
this evening.  How much room do you have left after implementing the
CIC in the FPGA?

73 de Phil N8VB

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