[hpsdr] "Taylor Corrected DDS"

[Alberto I2PHD]

Bob,

   ok, understood, I thought you were talking of the PC. I use the large table approach in Winrad and it works quite 
well. On a FPGA I agree it would be impractical, to say the least.

Do you know the Savage benchmark? Quite useful to evaluate both speed and accuracy of the floating point implementation 
on a given HW + FP Library combination. I can post it here if you want, it consists of only a few lines of code.

73  Alberto  I2PHD
--------------------------------

Robert McGwier wrote:
> Alberto:
> 
> You are correct.. But on my desktop, none of this is an issue.
> 
> The topic was about DDS's on FPGA's and possibly CPLD's.   2^18 complex 
> numbers at (say)  4 bytes each (2 bytes real,  2 bytes imaginary) giving 
> 1 MB of RAM required on the FPGA, might be a problem on a CPLD, it would 
> be a deal killer.
> 
> I found that on the desktop,   I could do one transcendental function 
> evaluation sequence and then run (using double precision)the simple 
> vector rotate to produce the I/Q output for days before any problems 
> creeped in.   The available dynamic range in the mantissa alone (forget 
> the exponent) is 288 dB and thought floating point error is creeping in 
> using this technique,   it is negligible until days have passed.  Once a 
> week,  you should turn on the oscillator and restart it.  ;-).
> 
> Bob

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