[hpsdr] Horton LO: Further thoughts

[Philip Covington]

On 6/17/06, Chris Bartram <chris at chris-bartram.co.uk> wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> I can see a few potential problems with Phil's proposal:
>
> a/ Trying to make a decent phase-frequency detector in an FPGA isn't going to
> be that easy.
>
> b/ you're handicapping yourselves by using a VHF VCO. To get the near octave
> tuning range required in a VHF VCO with low noise (even with pre-tuning)
> isn't easy, and you'll end-up with some critical analogue design problems.
>
> c/ The relatively large N-divider ratios will lead to worse close-in phase
> noise than might be possible.
>
> If I were trying to design a synth. for an HF receiver, I'd be very tempted to
> start with a VCO operating in the 2GHz region, and to use that within a loop
> controlled by a commodity synthesiser chip such as those produced by National
> or AD. I'd then use the N-divider of a second synth. chip to divide the
> locked VCO output to HF.
>
> My reasons for suggesting the use of synthesiser chips rather than the FPGA
> approach include:
>
> a/ the level of development of the PFDs - there's about three decades of
> engineering development residing in the current designs
>
> b/ the relatively good phase noise of the dividers - see above...
>
> c/ the potential to use a fractional/N part to get 'awkward' frequency
> spacings or to keep the reference frequency high, and consequently the N
> division ratio low.
>
> The downside is that it needs, maybe, a single extra package costing a couple
> of Euros, although it might be possible to use one of the dual synthesiser
> parts.
>
> Commodity VCO parts (using coaxial ceramic resonators) in the 2.4GHz region
> have phase noise in the region of -95dBc/Hz at 10kHz offset. Divided down to,
> say, 1.8MHz would give ~-160dBc at 10kHz (in practice that would probably be
> limited by the phase noise of the dividers) A simple VCO with a microstrip
> transmission line resonator printed on teflon/glass has given me about
> -105dBc/Hz/20kHz  at 1.872GHz in a VCO forming part of a 6cm transverter. The
> close-in phase noise at 5.7GHz, measured as spurious FM, was of the order of
> 10Hz in the audio band. The 'note' was entirely T9 at 6cm.
>
> Some of the more recent 'VCO-on-chip' parts from AD and National have VCO
> performance approaching that of the ceramic resonator VCOs.
>
> As a matter of interest, by using ceramic coaxial resonator or circular or
> rectangular cavities at microwave frequencies as VCO resonators, it's
> possible to get much higher unloaded Q than is possible by conventional L/C
> or coaxial line techniques at VHF. With proper design, that can lead to
> higher loaded Q from oscillator resonators, and thus better phase noise
> performance. See Leeson's paper, and later work. The limiting factor is often
> the Q of varactors. Notwithstanding that, a move to microwave VCOs could
> offer two routes to improved phase noise at HF and VHF.
>
> We'll probably be using a similar approach to that I've described, with a
> 2.4GHz commodity VCO, in the uWSDR group front-ends for 70, 144, and 432MHz.
>
> Vy 73
>
> Chris
> GW4DGU

Hi Chris,

In my original scheme I was going to use a National PLL instead of
using the FPGA/CPLD for a phase/freq detector as Phil depicts in the
document.  The CPLD would then divide down the locked VCO running in
the 100-200 MHz range.  I proposed using the CPLD as a quick way of
getting a programmable divider set via serial programming... but I had
not thought of the idea of using a second PLL chip's N divider to do
that function instead of the CPLD - I like your idea much better!

When we started talking about VCO's running in the microwave region, I
figured that we would just have some prescaling type dividers to get
down to where the CPLD would handle the rest ( < 300 MHz).  The big
question I had was how much jitter the prescale and CPLD dividers
would add.  By using the dividers on the National chip for that
function, I would assume that we could not get much better - because,
as you said, the engineering experience incorporated into those chips
over time.

Thanks for your expert comments... they have given me a lot to think about!

73 de Phil N8VB

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