[hpsdr] [OZY] Schematic update May 16, 2006

[Lyle Johnson]

Hello Phil!

> PDF Schematic at:
> 
> <http://www.philcovington.com/HPSDR/OZY/REVXA.3/>
> 
> Added Panasonic RC filter networks to the local IO on OZY.
> 
> Good news is that I will probably be able to add the 20 pin logic
> analyzer/debug port back into the design because of the space savings
> from using resistor networks and moving some of the passive components
> to the backside of the PCB.

:-)

One note: if the logic analyzer connector will include any of the lines 
between the FPGA and U14 (input buffer) it might be useful to have a 
jumper to enable U14's nOE.  That way the FPGA can set these as outputs 
and not have conflict with U14.

I also noticed that U16 nOE1 and U14 nOE1 are not connected.  They 
should probably tie to OE_PULLUP1 like U18.  And there needs to be a way 
to pull this line low to enable the buffers. It may be there and I just 
am not seeing it.  I believe the logic is such that nOE1 and nOE2 must 
both be pulled low to enable the '541 buffer.

73,

Lyle KK7P


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