[hpsdr] OZY REVB Going once...going twice...

[Lyle Johnson]

Hello Phil!

I've checked the schematic against the list of changes and reviewed the 
PCB layout. The layout review was at a pretty ,macro level as the board 
is very complex, and based on the success of the previous board I have 
more trust in the auto router than time to check the nets :-)

Anyway, I observe the following:

1) For EP2C8 compatibility, pins 32 and 120 of the FPGA are tied to 
+1V2.  Will this result in high current through the chip if the EP2C5 is 
used and these then become CMOS inputs on a 3V3 IO??

2) The Ozy errata lists pins 103 and 104 as RXD/TXD, but the schematic 
shows 101 and 102 as these functions, with 103 and 104 being A31 and A29.

3) Some of the traces on the PCB look *awfully* tight.  For example, the 
top layer trace that wraps around R18 pin 10 seems too close to the 
corners of the pad.

4) I see some adjacent ins are tied together in the middle of the pin 
pads instead of away from the pin area of the pads.  For example, the 
FPGA pins 49-50, and 54-55 (if I counted them correctly).

73,

Lyle KK7P


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