[hpsdr] Digital Down Converter design

Philip Covington p.covington at gmail.com
Thu Sep 7 04:43:40 PDT 2006


On 9/6/06, Darrell Harmon <dlharmon at dlharmon.com> wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> I have been working on a DDC core for my spectrum analyzer project.
> The verilog source will be released under the GPL. I though it might
> be usable for the HPSDR project as well. If anyone is interested, I
> can make minor changes to the core to fit your needs. I have written
> the Verilog, done simple tests, and synthesized the core in Xilinx
> ISE successfully. It still needs some minor tweaking and more testing.
>
> The core consists of a CORDIC NCO/mixer, a CIC filter and a decimating
> programmable FIR filter. The datapath grows from 16 bits at the input
> to 18 bits at the output for increased dynamic range. The current
> CIC filter has a fixed decimation rate of 25, but I plan to redo it
> with a variable decimation rate of 8 to 1024. The FIR can do any
> decimation rate with some limitations. The coefficients are 18 bits
> and the filter performs 1 MAC/clock cycle. The impulse response can
> be up to 512 points.
>
> Resource utilization (Current version)
> 1042 Xilinx slices
> 2 block rams (18 kbit)
> 2 18x18 multipliers
> This all fits in an XC3S200 ($15, TQFP144) with plenty of room to
> spare. I will be using an XC3S1000 as I will probably use multiple
> channels.
>
> The maximum clock rate is 150 MHz. I am clocking at 125 MHz.
>
> The dynamic range should be around 95 to 100 dB. This could be
> improved by using more resources.
>
> It will be a while until I get hardware since I want to get the
> FPGA done first. I still need to implement a FFT and a DUC.
> My board transmits too.
>
> The verilog is in a Subversion repository at
> svn://dlharmon.com/analyzer/trunk/verilog
> The code is a mess right now, and needs some documentation.
>
> This DDC may not be very appropriate for Mercury, but I thought I
> would offer.
>
> --
> Darrell Harmon
> http://dlharmon.com

Hi Darrell,

Thanks for making your verilog available.  It will help to have some
more code to look over in our quest for the correct arrangement of the
Mercury DDC.

73 de Phil N8VB

 1157629420.0


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