[hpsdr] Odissey QSD circuit diagram

[Marco]

At 22.42 29/09/2006, jim ab3cv wrote:

>I was looking at Phil's circuit and can't figure out something. IIRC, in
>order for the integrator summing junction to function the signals applied
>need to be within the loopgain of the integrator.
>
>The signals applied to the integrator are the sum and difference freqs (and
>harmonics) of the received signal and the vfo.
>
>I don't see how the sum frequencies are handled by the integrator since they
>exceed the available loop gain. Are they merely passed through to the
>passive filter that is behind the opa1632?
>
>If so how then does this act to maintain the proper impedence mentioned
>below?
>
>tnx
>jim ab3cv

I agree with Jim. I have another concern: that switching transient 
and out-of-band signals and harmonics, extending in the UHF/GHz 
range, may cause non linearities in the input transistors of the 
opamp. Outside the loop band the mixer sees the opamp's input 
capacitance in parallel with the output impedance. The output Z is 
specified in the OPA1632 data sheet, and is quite high. The input 
stage of the OPA my be driven in saturation/interdition by the 
switching transients.

Possibly a different termination may be studied. By instance, 
splitting the 93 Ohm resistance between input and output of the 
switch, and implementing a low-pass filter acting as VHF/UHF 
termination between the switch and the OPA. Or possibly a true diplexer?

Im my opinion, some experimentation is necessary here. I ordered two 
more SR V6 kits. I want to use them as clock generators, do some IMD 
and dynamic range tests, and measure the transients after the 
proposed mixer. The input/output capacitances of those switches are 
in the 3-15pF range, and so some transient coupling can't be avoided.

73 - Marco IK1ODO



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