[hpsdr] sampling
Lawrence D. Lopez
lopez at mv.mv.com
Sun Apr 22 08:28:43 PDT 2007
i was under the impression that sdr over sampled using low precision
a/d converters in order to gain higher a/d accuracy.
For instrance:
a 16 bit a/d with .1 volt full scale has a resolution of 1.5 micro volts.
Which is pretty useless.
jeff millar wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> FRANCIS CARCIA wrote:
>
>> Say you sample 30 mhz at 60 mhz rate and you just happen to convert on
>> the zero cross at 0 and 180 degrees. What information will you get? I
>> would think you would need to sample at least 4 times to catch real
>> information. Heck we sample audio at 192 khz these days so why ? That is
>> at least 10 samples per highest audio frequency. Frank and other
>> grasshoppers???
>>
>
> Widipedia answers this question well
>
> http://en.wikipedia.org/wiki/Nyquist_sampling#The_sampling_process
>
> Note that if the original signal contains a frequency component
> exactly equal to one-half the sampling rate, this condition is
> not satisfied, and the resulting reconstructed signal may have
> a component at that frequency but the amplitude and phase of
> that component will not, in general, match the original component.
>
> Generally, real systems sample with two A/Ds 90 degrees out of phase
> (I/Q), which captures amplitude information. If one sample stream
> happens to fall on the zeros, the other falls on the peaks.
>
> It really important to get past the idea that you need a lot of
> samples to reconstruct the signal. Because, SDR will often use
> input signals above 1/2 of sampling frequency. The theorem states
> that
> “Exact reconstruction of a continuous-time baseband signal
> from its samples is possible if the signal is bandlimited
> and the sampling frequency is greater than twice the
> _signal bandwidth_."
>
> This statement allows signals anywhere in the spectrum, including
> spreading across the clock frequency or it's harmonics.
>
> Modern A/D's support sampling inputs signals much higher than
> their clock frequency. The designer must bandlimit the input
> signal to less than 1/2 the clock frequency.
>
> jeff, wa1hco
> _______________________________________________
> HPSDR Discussion List
> To post msg: hpsdr at hpsdr.org
> Subscription help: http://lists.hpsdr.org/listinfo.cgi/hpsdr-hpsdr.org
> HPSDR web page: http://hpsdr.org
> Archives: http://lists.hpsdr.org/pipermail/hpsdr-hpsdr.org/
>
>
1177255723.0
More information about the Hpsdr
mailing list