[hpsdr] Blackfin 32*32 bits multiply

[Chris Down]

On 21/08/2007, Chris Donzelot wrote:

> There is some details in the Blackfin Hardware reference.
> The 32bits mpy is microcoded
> The dual MAC operation only allow doubling MAC throughput , you can
> input two 32 bits scalar into both MACs to double throughput.
> One of both MAC have a shifter just after accumulator, and the MAC
> output can be a standard  32 bits register.
> The  32 bits  MAC will be slower than 300 MMAC/s @ 600 MHz (4 16x16 MAC
> + shift & 32 bits addition).
>

I am not an expert in the Blackfin, however I have been reading up on it.
Some Blackfin instructions can be performed in parallel thereby reducing the
number of cycles.

If you look at Analog Devices, Engineer to Engineer Note EE-186
(http://www.analog.com/UploadedFiles/Application_Notes/52064380701163EE186.p
df ), you will see that it is possible  to do a 32 x 32 multiply with a 31
bit accuracy in 2 instructions cycles.

Also in the same document are examples of 32 bit and 31 bit accurate FIR
implementations with a calculation for the number of cycles. This may help
estimate the relative performance of the Blackfin against a Pentium. I do
not know the equivalent number of cycles for Pentium type processor, perhaps
some else could point to a source for these.

Of course the time taken to carry out a 32 bit multiply is only part of the
story. Perhaps a better solution would be to choose a particular dsp
function or set of functions required and do a direct comparison.

Chris Down
G8MXW


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