[hpsdr] Blackfin 32*32 bits multiply

[Robert McGwier]

But an even more important feature of the 32x32 bit multipliers and 
larger accumulators (and this was true of the DSP56000, 24 bit 
architectre and others) is that the actual instruction used for doing 
FIR filters is much more than just a multiply.  It does multiply, add 
the result to the larger accumulator,  reads in the next coefficient and 
the next piece of data from the buffers, etc., does modulo arithmetic on 
these buffer pointers and accomplishes ALL of this in ONE instruction.

Now add to this the complication in the current TI family of very long 
instruction words and the need to optimize the order of instructions and 
it becomes apparent why the expensive development tools are required. It 
is nearly impossible to optimize this by hand, even if you are writing 
directly for the assembler.

Bob

> Philip Covington wrote:
>> ***** High Performance Software Defined Radio Discussion List *****
>>
>> On 8/21/07, Greg Overkamp <overkamp at yahoo.com> wrote:
>>   
>>> ***** High Performance Software Defined Radio Discussion List *****
>>>
>>> A 32x32 bit multiply produces a 64-bit result. In the
>>>     
>>> case of the Blackfin 32x32 bit multiply (I am
>>> referring to the built-in 32x32 bit multiply, not one
>>> that you would write yourself as a macro) the result
>>> can only be saved to a 32-bit register. This means
>>> that you would need to scale down either the
>>> coefficients or the data in order to prevent overflow
>>> on storing the multiplier result, which really defeats
>>> the purpose of having a 32x32 bit multiply.
>>>
>>> Most integer DSPs have accumulators that are even
>>> larger than the multiply result, which allows the
>>> intermediate sum-of-products in an FIR filter, for
>>> example, to grow larger than the size of the multiply
>>> result (64-bits in the case of a 32x32 bit multiply).
>>> The final FIR result may be within range of the size
>>> of the multiplier output width, while the intermediate
>>> sum could have grown larger than this width. The extra
>>> accumulator width prevents saturation from occurring
>>> during the sum-of-products. The Blackfin does indeed
>>> do this for its 16x16 bit multiply by providing a
>>> 40-bit accumulator rather than a 32-bit accumulator
>>> (recall the Motorola DSP56000 with its 24x24
>>> multiplier and 56-bit accumulator).
>>>
>>> A 32x32 bit multiply with a 32-bit result is only
>>> useful if you know ahead of time that either your data
>>> or your coefficients will not be 32 bits. When using
>>> 24-bit data converters, you would have to use 8-bit
>>> FIR coefficients in order to guarantee no overflow of
>>> the multiplier! I really think that application note
>>> EE-186 is wishful thinking on ADI's part in order to
>>> try to sell its Blackfin processor to audio folks.
>>>
>>> The Blackfin looks like a great 16-bit DSP, but for
>>> high resolution audio work (or baseband SDR using
>>> 24-bit converters) I think a better choice would be a
>>> DSP that has native 32-bit arithmetic.
>>>
>>> Greg
>>> WD9DEX
>>>     
>> Thanks Greg! FINALLY someone talking some sense about the Blackfin (as
>> opposed to the armchair DSP engineers)!
>>
>> 73 Phil N8VB
>> _______________________________________________


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