[hpsdr] Verilog vs VHDL

[Steven Wilson]

I'm going to take a crack at answering you in a different way. 

Do you know C? 

If so - then likely Verilog is more your cup of tea and would be far
easier to learn than VHDL. 

However, if you are a fan of strongly typed languages that protect you -
the VHDL is more likely what you'll take a liking too.  VHDL is very
much a descendant of ADA.

For a QUICK look at both languages, try looking at the Wikipedia entry
for both.  Both entries talk about hardware realizations of logic. This
gives you an idea of how you have to code things to get the type of
hardware constructs you're after.

For my own tastes - hardware itself can usually be expressed more
concisely with Verilog (less lines of code...) As the Wikipedia article
on VHDL comments - there is a constantly raging VHDL/Verilog war as to
which is best. In reality, it likely depends a bit more on your
background as to which you'd most easily pick up.

Hope that gives you a starting place.

Steve KA6S  (professional Verilog coder... ;-)


k5nwa wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> Which is more user friendly? I'm trying to decide between Verilog and 
> VHDL for a FPGA project and wanted some opinions on the subject 
> before I go out and spend some money on books. The project will 
> involve mostly processing of I/Q audio streams and some video display 
> control, so a big issue will be math processing.
>
> I'm leaning heavily towards Verilog since it seems less wordy than 
> VHDL, and there are some in this group that are familiar with it.
>
> Any thoughts?
>
> Cecil
> KD5NWA
> www.softrockradio.org  www.qrpradio.com
>
> "Blessed are the cracked, for they shall let in the light."  
>
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