[hpsdr] HPSDR Mercury Info

[Philip Covington]

Hi all,

I thought I would post some more information about the HPSDR Mercury
board since, from listening to the Teamspeak session on Saturday,
there appears to be some confusion about details of the board.

The Mercury will use a LTC2208 16 bit 130 MSPS ADC.  The ADC will be
run at 125 MSPS since it is much easier to get 125 MHz ultra low phase
noise VCXOs.  I am currently using a Crystek VCXO model CVHD-950
(Ultra-Low Phase Noise -162dBc/Hz Typical Floor).  These are available
from Mouser and are typically in stock.  They are not inexpensive ($42
ea) but do have low phase noise characteristics we need for the ADC
encode clock.  Running the LTC2208 at 125 MHz will give Mercury a
range of 0.1-55 MHz - the low end is limited by the frequency response
of the transformer input to the ADC (typically 100-300 kHz).

The RF front end will consist of a bypass-able Bandpass filter with a
fc of 1.5 MHz followed by a bypass-able Lowpass filter with a fc of 55
MHz.

Following the BPF and LPF will be a programmable Attenuator that can
be digitally set in 0.5 dB steps from 0-31.5 dB attenuation.

<http://www.hittite.com/product_info/product_specs/attenuators/hmc472lp4.pdf>

Following the attenuator are two bypass-able 15 dB low noise RF Amps.
The RF amps we are using are Sirenza devices that I found and used in
the QuickSilver QS1R prototype.  Currently in QS1R I am using the
SBF-5089 device with a gain of 20 dB and a NF of 2.8 dB.

<http://www.sirenza.com/default.aspx?pageid=31&categoryid=10&productid=SBF-5089>

>From testing with the QS1R prototype, I have found that a little more
gain would be desirable above 20 MHz so we decided to cascade two
bypass-able 15 dB stages to be able to select 0 dB, 15 dB, or 30 dB of
RF gain.  The devices that we intend to use are the SBF-4089 with a NF
of 3.3 dB:

<http://www.sirenza.com/default.aspx?pageid=31&categoryid=10&productid=SBF-4089>

I have tried some other Sirenza SGA series devices in the QS1R prototype:

<http://www.sirenza.com/default.aspx?pageid=31&categoryid=10>

and have found that their gain in the 0-30 MHz range is not specified
and, in practice, tends to be about 3-5 dB less than their specified
gain at higher frequencies (>500 MHz).  The SBF series seems to work
well for our purposes and they maintain their specified gain over the
0-55 MHz range.  The Sirenza devices are stocked by Digikey and
typically cost around $2-3 in single quantities.

Each of the above stages (BPF, LPF, ATTEN, RF AMP 1 & 2) can be
bypassed.  We are going to use the same switches that I chose for
QuickSilver QS1R:

<http://www.hittite.com/product_info/product_specs/switches/hmc226.pdf>

We will use the output randomizer feature of the LTC2208 ADC to reduce
tones appearing within out sampled bandwidth due to digital noise on
the ADC output bus.  This have been tested in the QS1R prototype and I
do see a worthwhile reduction of tones with this feature turned on.

The Digital Down-conversion (DDC) function will be done in the FPGA.
Without going into the details of CIC filters and their compensation
filters, there is enough room for most of the filtering and
down-sampling functions in the FPGA except for the final step.  We
need a compensation filter of about 300-512 taps for both the I and Q
data paths.  Filters of this size require a larger and more expensive
FPGA to have enough Logical Elements (LEs) or Multipliers (MACs)  to
implement them.

Instead I have found a company that makes a serial FIR engine in a 3mm
x 3mm QFN package:

<http://www.quickfiltertech.com/html/qfilter_page.php?content_id=45>

These chips will allow us to load in our own filter coefficients and
will work up 500 kSPS with 24 bit serial data.  These chips will be
used as FIR co-processors connected to the FPGA to do the final
compensation filtering and down sampling to 192, 96, or 48 kHz (or any
other rate below 500 kSPS).  I have two of the Quickfilter DIP
prototyping boards that I am using with QS1R to do the initial
testing.  If all goes well, four of these chips will be used on
Mercury.  This will allow either two separate receiver chains or a
single chain of up to 1 MSPS rate.

In addition to real-time streaming at rates below 1 MSPS, Mercury will
support spectrum analyzer mode where the complete 0-55 MHz spectrum
can be viewed in snapshots.  These snapshots can be updated at rates
of up to 10 ms per acquisition - so to the eye they appear to be
real-time on the spectrum display.

Mercury will also support a stream to disk mode where digitized date
of large bandwidths (1 - 10 MHz) can be streamed to disk and then
later played back at lower rates.

Since the FPGA is programmable I am sure others will come up with
features that we cannot envision now.

I hope this helps people in trying to understand the Mercury board.

73 Phil N8VB