[hpsdr] HPSDR - Penelope update

[Christopher T. Day]

Phil,

You're probably already planning it this way, but just to be sure the
idea is out there...

Looking at Penelope and playing around with the Janus CPLD has got me
thinking. It looks to me as though Penelope has the hardware, sans DSP,
for a complete TX chain, i.e., audio ADCs in the on-board TI
TLV320AIC23B for getting bits from a microphone or line-in onto Atlas
for the DSP, and the RF DAC to get the bits at "audio" or "if" from
Atlas to the antenna. How about putting another one of the
TLV320AIC23Bs, since they are now familiar, onto Mercury so that it is a
matching full RX chain? I.e., the fast ADC gets the RF down to "audio"
or "if" and onto Atlas, and the TI takes the processed bits and squirts
it out the nice headphone amplifier.

I think this would make for a nice mix-and-match setup. An SWL person
could get only Mercury and Ozy and have a complete system for his needs.
An SDR-1000 owner could use Janus and Ozy. A total digital freak could
go with Mercury, Penelope and Ozy. Surely there is some excuse for a
Penelope/Ozy only system as well.

As I say, pretty obvious, but looking at the split of functionality
between the JanusCPLD and the OzyFPGA, it might be worth thinking about
moving some items from Ozy to Janus. For example, if the PWM DACs were
moved from Oxy to Janus and accessed over another I2S, then Ozy would
hardly notice if that I2S drove the TI chip on Penelope instead.
Likewise, making Janus responsible for resetting its own AK5394A could
again make Ozy not care who's on the other end.

Too late for round one of Janus/Oxy, but maybe worth thinking about for
firmware upgrades?


	Chris - AE6VK


-----Original Message-----
From: pvharman at arach.net.au [mailto:pvharman at arach.net.au] 
Sent: Wednesday, February 07, 2007 7:38 PM
To: hpsdr at hpsdr.org
Subject: [hpsdr] HPSDR - Penelope update

***** High Performance Software Defined Radio Discussion List *****

All,

I've just updated the block diagram of Penelope on the Wiki

< http://hpsdr.org/wiki/index.php?title=PENELOPE#PENELOPE_-
_Companion_Transmitter_to_Mercury >

The latest block diagram reflects the current breadboard prototype. 

The performance looks very good.  Harmonic content is very low and DDS
spurs 
are well below the FCC specifications. 

Carrier suppression and unwanted sideband suppression also seem
excellent, at 
the moment the measurement is  limited by the dynamic range of my
spectrum 
analyzer. 

I've also tested creating AM and FM in the FPGA rather then using the
11kHz 
signal from PowerSDR.  This seems to work fine and eliminates any image
issues 
due  to imperfect I & Q  balance. 

Bill, KD5TFD, has modified PowerSDR to provide the RF envelope and
carrier 
phase outputs that will be needed for a future  Envelope Elimination and

Restoration (EER) power amplifier.  If anyone would like to assist in
the 
development of such an amplifier please drop me an email. 

We are now moving to a prototype PCB which Lyle, KK7P, is designing. 

There is still a small window to add features so please review the
latest block 
diagram and lets us have your ideas and suggestions ASAP. 

73's Phil....VK6APH 

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