[hpsdr] Ozy and Janus code updated

[Phil Harman]

Based on Chris, AE6VK, suggestion I have moved the PWM DAC from the Ozy FPGA 
to  the Janus CPLD. The I and Q data in now sent in I2S format over the 
Atlas bus and can be used by Penelope also. Thanks for the suggestion Chris.

I've also add the 48MHz FX2 clock to Atlas for use by the PWM DAC in Janus. 
I'd really like to run the DAC faster to give a littel more resolution but 
since the CPLD does not have any PLLs and it is now 80% full then we are 
going to need a simple clock multiplier to achieve this. Any ideas or 
suggestions?

New Verilog files are in SVN and I've updated the Atlas pins designations in 
the spreadsheet in the Altas folder.

73's Phil...VK6APH



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