[hpsdr] ALEX - Call for Comments - III

[Lyle Johnson]

Hello Graham!

> 2.) Control...
> Lyle's KK7P comments on control lines allowing coupling to the
> input and output of the filters and allowing "filter bypass"
> are noted.
> 
> A question for Lyle or Phil C or someone familiar with the CPLD parts...
> If I don't care about output rise and fall time, what is the
> largest capacitor (I am thinking 0.01 uF or 0.1 uF, .01 ohm ESR)
> that I can throw on the output line of a CPLD?  Will it current
> limit and protect itself until the capacitor charges, or will
> it trigger life issues after repetitive cycling?

Please use series R next to the CPLD pin and then a bypass C if your 
goal is to slow an output from the CPLD, series R and then C at the DIN 
connector to slow input edges, and a T (series R - shunt C - series R at 
the DIN to slow a bidirectional pin.

Don't put anything to mess with edges on the JTAG pins!  They normally 
will be dormant anyway, so shouldn't cause any operational noise.

73,

Lyle KK7P


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