[hpsdr] ALEX - Call for Comments - III

[Graham Haddock]

pvharman at arach.net.au wrote:
> In terms of series R, how much can we allow before the RF switches complain?
>
> Phil....VK6APH 
>
>
>
> Quoting Lyle Johnson <kk7p at wavecable.com>:
>
>
> Hello Graham!
>
>   
>>> 2.) Control...
>>>
>>> A question for Lyle or Phil C or someone familiar with the CPLD parts...
>>> If I don't care about output rise and fall time, what is the
>>> largest capacitor (I am thinking 0.01 uF or 0.1 uF, .01 ohm ESR)
>>> that I can throw on the output line of a CPLD?  Will it current
>>> limit and protect itself until the capacitor charges, or will
>>> it trigger life issues after repetitive cycling?
>>>       
>> Please use series R next to the CPLD pin and then a bypass C if your 
>> goal is to slow an output from the CPLD, series R and then C at the DIN 
>> connector to slow input edges, and a T (series R - shunt C - series R at 
>> the DIN to slow a bidirectional pin.
>>
>> Don't put anything to mess with edges on the JTAG pins!  They normally 
>> will be dormant anyway, so shouldn't cause any operational noise.
>>     
JTAG is not the issue at all.
I want to put several RF bypass capacitors on the lines that are the 
input to the RF Switches,
to try to bypass any RF that might couple to the lines.  Putting a 
series 100R between
the CPLD output and the bypass caps should not be a problem, I just wanted
to know if I could do without them.  The RF Switches
should not care, since I assume we are looking into the gate of a FET, and
approximately infinite input impedance.  Time to switch filter sections will
be "slowed down" to a few hundred microseconds.  ;-)

--- Graham



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