[hpsdr] TAPR

[Bill Tracey]

Hello Frank,

The testing setup that Scotty and crew were using takes a bit of work 
to setup.  For the Ozy board there's a loopback  FPGA image in SVN 
under KD5TFD/OzyWrapTest.  The FPGA image depends on a bunch of the 
Atlas and GPIO lines being connected to each other - essentially the 
code puts a signal out on one line and sees if it gets it back on 
another line.  The lines that need to be connected together can be 
seen from the .xls file in SVN or from the WrapTest.v verilog 
code.   This test is typically loaded into the EP4CS ROM and run from 
there - no PC connection is needed.  A serial port is connected to 
the FPGA serial header at 115.2 kbps to get report of pass or 
fail.  In the case of failure, the circuit(s) failing are reported on 
the serial port.

I believe there's a similar image for the CPLD on Janus -- don't know 
the details on that one since I did not write it.

The other part of the test is a PC program - JanusTester that depends 
on the analog ins and outs on Janus being connected.  It pumps a 
signal out the D/A side and reads it back on on the A/D side and 
reports results for various test frequencies, aplitudes and sampling 
rates.  This code is SVN at KD5TFD/JanusTester.  This is a much more 
and end to end test as it goes to/from the PC and thru all the major 
pieces of Janus and Ozy.

Hope some of this is useful -- I'll admit to not writing much 
documentation on this stuff - but do try to make sure I get all the 
code published and will try and answer questions on it.

Cheers,

Bill (kd5tfd)


At 06:06 PM 5/2/2007, FRANCIS CARCIA wrote:
>***** High Performance Software Defined Radio Discussion List *****
>
>I would like to thank TAPR for their efforts as the hub of the wheel.
>it would be great ot be able to duplicate the testing for future 
>reference if something goes wrong. a simple procedure would also be 
>nice...please? frank.



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