[hpsdr] Will there be a Developers guide to HPSDR?

[Jason Hitesman]

On 5/20/07, Bill Tracey <bill at ewjt.com> wrote:
> Answers to some of your questions:

Thanks for the answer Bill, they're very helpful and more than I was
expecting this quickly!

> Q: Will there be a developers guide?
>
> A: Don't know -- I don't plan on writing one, I've got too many other
> things to do and I hate to write.  Willing to answer questions, etc
> on the mailing list but  I won't be authoring a comprehensive
> guide.   I'd certainly support someone or a group that wanted to take
> on a how to develop with Ozy

While I don't have enough knowledge to tackle a guide myself (at least
not yet) I will try to keep track of the various answers I do receive
so if I do reach a point where I have enough knowledge to be dangerous
I'll be able to share it with others.  As you may have noticed from my
e-mail I'm not exactly slow on the keyboard or have much of a dislike
of writing.  Heck that's why I'm not a big fan of most digital modes
and CW (at least CW at the speed I can handle!)....I get bored between
characters and loose my concentration!

The SVN references you provided are a great start since as I already
noticed the source I was able to find was well commented.

I do have a few questions about some of the sub-projects though.

> Janus CPLD code:
> svn://206.216.146.154/svn/repos_sdr_hpsdr/trunk/Janus-CPLDV2 -
> Sources and binary   This is seutp as a Quartus project - open
> Janus.qpf in Quartus

So is this separate from the code in the trunk/OzyV2-JanusV2
directory?  Or does the OzyV2-JanusV2 build upon what's in this
directory?  Since I don't have a functional Janus yet I'm a little in
the dark other than what I've been able to infer from various
discussions and the operating manual.

If this is separate from the code in OzyV2-JanusV2 then how does this
code get loaded into the Janus.  Will I need a byteblaster?  Or can it
be loaded through Ozy somehow?  Did this come pre-loaded on the
pre-assembled cards?   From what I understand CPLD's unlike FPGA's do
have non-volatile configuration so that may be what's confusing me.


So am I right in understanding that:

OzyV2-JanusV2 - Code for Ozy that includes code for interacting with
Janus - must be loaded each time the board is powered up.

Janus-CPLDV2 - Code for Janus that is loaded once.

If so I guess my big question is should I start planning on a
Byteblaster to program my Janus with or is there a way that it can be
done through Ozys USB connection?

> FX2 source code:
> svn://206.216.146.154/svn/repos_sdr_hpsdr/trunk/KD5TFD/Ozy-FX2-SDR1K-Control

Ahh, I had found that once but couldn't remember where I saw it!
Guess I'll have to blow the dust off of Eclipse and take a look!

> Various Utilities (load_firmware and friends):
> svn://206.216.146.154/svn/repos_sdr_hpsdr/trunk/N8VB/OZY_V1 - Source
> and binaries for Phil Covington's Ozy utilities, original FX2

Ah ha!  This is some of what I've been digging for an unable to find!
I didn't think to look in a directory with "V1" in it's name since I
was afraid it would be old code for the original beta boards.  This is
also some of what I'm most interested in since it covers talking to
the I2C bus from the computer.

> Probably more than most wanted to know, and make the project look
> dautning -- it's really not -- just a bit spread out.

Not too much at all!  That answered many of my questions...and gave me
keys to answer some of the rest myself!

> Will try and answer some more of your questions a bit later -- have
> to get on to some other errands at the moment.

No problem, what you've given me already tosses plenty of code in
front of my eyes to eat up my spare time for the entire week I'm sure
:D

I would still like some guidance on "baby steps" with Quartus and FPGA
"programming" so I can start getting my feet wet with that....but I
may be able to figure some of that out myself now.  I figure if
nothing else I can always compile what I learn and share it here for
peer-review to see if I'm way off base or on the right track.

One other thing I'm still unclear on.  In the Ozy block diagram I do
see a boot flash memory that appears to be for the FPGA....looking at
the schematic I think this is the 24c128 if I'm reading them right
(hard to say though since my printouts are so small!)

Like I said I'm new to the world of FPGA's so I'm hoping someone will
correct me if I'm wrong..but I was under the impression that this
would enable the board to load the FPGA itself negating the need to
re-load the firmware each time we want to use our boards as we do now.

I could go on with more questions related to the boot process...but I
think a lot of my questions would answer themselves if I was more
clear on what the flash memory is being used for and what it's capable
of.

Thanks again for the help so far!  Your reply was very beneficial and
has given me a lot of starting points to learn more - and that's
really what I wanted the most!

-----
Jason Hitesman
N8INJ

 1179687866.0