[hpsdr] Fixed Saw Oscillators

[Grant Hodgson]

There are lots of different ways to get a 1GHz or so clock for the new
generation DDSs.

There is no universal 'best' way to generate the clock, as there are 
many different requirements from many different users for different 
applications.

The lowest phase noise approach would probably be as Chris GW4DGU has 
stated, which is to use a VHF crystal oscillator with a low noise 
multiplier, but in order to get very low spurs (of the clock 
sub-harmonics) a high degree of filtering is required, which as has 
already been mentioned, is not a trivial task.

A SAW oscillator is indeed an alternative approach, which has the 
advantages of elegance and simplicity, but does not have the best 
close-in phase noise, and would appear to be significantly worse than 
the PLL approach mentioned below.  The SAW oscillator could be 
referenced to an OCXO or other reference, which should be able to 
improve the close-in phase noise at the cost of extra complexity.

My belief based on system calculations and data from manufacturer's data 
sheets (which are usually very reliable nowadays) is that for the 
purposes of HF communications, using the AD9912's on-chip PLL clock 
multiplier with a (very) good VHF crystal oscillator will
give a DDS clock that will result in a system with close in phase noise 
performance that is better than just about any other radio available 
today.  The VHF crystal oscillator could be locked to an OCXO or GPS if 
required for extra stability, but I'm not sure if that would 
significantly improve the close-in phase noise performance - the 9912 
would then become the limiting factor.

I've already done some measurements on the AD9910, which is similar to 
the AD9912 in some respects, and which appears to meet or exceed the 
manufacturer's claims.  I'm hoping to do some measurements on the 9912 
soon, which it would seem should be even better than the 9912.

For the non-believers, and those familiar with DDS chips such as the 
9852/9951 etc., it is worth pointing out that the performance of the 
9912's on-chip PLL is far better than any other PLL-based clock 
multiplier used on previous DDS chips; this alone represents a 
significant improvement in system performance.  Coupled with the 
unsurpassed close-in spur performance of the 9912, the option of a 
DDS-based LO for a high performance receiver not only becomes feasible, 
it would seem to be THE way to go.  And that statement is based on doing 
detailed system calculations for other LO schemes, particularly the 
option of a very high-performance microwave PLL approach - which doesn't 
appear to be as good as the DDS approach.

But that's just my opinion - I'm happy to co-exist with others that have 
different requirements and opinions; there may yet be other approaches 
that may be more suitable.

regards

Grant G8UBN

> 
> When I worked at Andersen Labs we thought we were doing a good job if a 
> 1 GHz saw oscilltaor only drifted 50 kHz. over the mil temperature 
> range. I wouldn't even consider it for a radio reference.
> The VCSOs have an active phase shifter in the loop to pull the 
> oscillator. I would like to know how a DDS can multiply a clock by 8 and 
> not degrade close in phase noise? Frank
> 
> ------------------------------------------------------------------------


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