[hpsdr] Penelope - external 10MHz reference input

[Phil Harman]

>From emails received I see that a number of folks are experimenting with 
feeding an external 10MHz reference into the Atlas bus at C16 in order to 
phase lock the 122.88MHz VCXO.

Please bear in mind a couple of things:

1. The FPGA is running off a 3.3v supply, hence the external input should be 
limited to this level. The FPGA may survive a 5v p-p TTL input but I've not 
checked this on the data sheet. If you have a TTL level source then use a 
resitive divider to drop this to 3.3v p-p.

2. The divide by 125 code in the FPGA needs a nice clean squarewave to work 
correctly. Check your waveform at C16 using a very short ground lead on the 
'scope and a x10 probe. If the signal does not look clean, and with  a nice 
sharp leading edge, then the odds are its not going to work correctly.

For those experimenting with this feature of Penelope I can provide a 
special version of the FPGA code that feeds the inputs to the PLL phase 
detector to some spare pins on the Atlas bus. That way you can check your 
external reference is driving the bus correctly. You will need a JTAG 
programmer to try this code. Alternatively, the Penelope source code is in 
SVN so feel free to try this yourself.

I have tested feeding the 10MHz TCXO from the Alpha Mercury board over the 
bus to Penelope to simulate an external clock and it works fine.

As I mentioned in a previous post,  we will be developing a small Atlas 
board that will take an external high accuracy clock and buffer it correctly 
to drive the bus.

73's Phil....VK6APH







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