[hpsdr] Fw: multiple receivers - is it really necessary

[Bob McGwier]

It is not even half full and this is as I expected it would be.

I am wondering if the FPGA experts here can answer the following question.

Can we implement a 512 point complex FFT running once every 1024 samples 
(decimated from the full rate or not and only needed to run > 60 msps)?

If the answer to this is yes,  can we run 1024  4 or 5 taps filters 
running in parallel once every 1024 samples?

If so,  we can replace the guts with a full polyphase filter bank 
implementation and channelize the ENTIRE HF SPECTRUM in 30 kHz bands 
(very high SFDR) which can be sent to computer as needed and recombined 
(synthesized) to make up whole bands.  The USB port in Ozzie/Mercury 
will support many MHz of bandwidth.  We need < 4 MHz to not drop a 
single Hz of HF. 

I am not an FPGA programmer.  I will lead one to the implementation if 
we so choose.  fred harris and I have perfected the variable bandwidth 
polyphase filter bank channelizer (and will be the topic for our SDR 
Forum paper in a couple of months) while I cannot give this paper out 
until the conference is concluded (that is the agreement you make), it 
will be okay to give it to a working partner.

I will specify a complete design in octave/matlab so others can run it 
and see it work if I get an FPGA partner to implement it.

Bob


Steve Bunch wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
>   
>
> ------------------------------------------------------------------------
>
> In the svn repository, Mercury 2.7 directory, file Mercury.fit.rpt 
> says (trimmed):
>
> ; Fitter Summary
>
> ; Fitter Status    Successful - Mon May 18 19:06:55 2009
> ; Quartus II Version    ; 9.0 Build 132 02/25/2009 SJ Web Edition ;
> ; Revision Name    ; Mercury
> ; Top-level Entity Name    ; Mercury
> ; Family    ; Cyclone III
> ; Device    ; EP3C25Q240C8
> ; Timing Models    ; Final
> ; Total logic elements    ; 9,653 / 24,624 ( 39 % )
> ;     Total combinational functions    ; 7,828 / 24,624 ( 32 % )
> ;     Dedicated logic registers    ; 7,470 / 24,624 ( 30 % )
> ; Total registers    ; 7470
> ; Total pins    ; 61 / 149 ( 41 % )
> ; Total virtual pins    ; 0
> ; Total memory bits     ; 84,380 / 608,256 ( 14 % )
> ; Embedded Multiplier 9-bit elements ; 22 / 132 ( 17 % )
> ; Total PLLs     ; 0 / 4 ( 0 % )
>
> More detail is there in the rest of the report - search down for 
> "Fitter Resource Utilization by Entity".  It looks like the receiver 
> entity is about 80% of the total gates.  So there's room for one or 
> maybe barely two more identical receivers without any material change 
> to the receiver design.  With some optimization, like using NCO's that 
> use COS lookup and interpolation instead of CORDIC to take advantage 
> of the unused memory and multipliers (Xilinx's library NCO cell does 
> this, I haven't looked at Altera's), or changing the performance specs 
> of secondary receivers to use fewer filter resources, you could 
> probably get more than that.
>
> The other cards are also in the SVN, have a look!
>
> Steve, K9SRB
>
> ------------------------------------------------------------------------
> **
> 2009/8/3 alex <ajbr at btconnect.com <mailto:ajbr at btconnect.com>>:
> >
> > i thought we were running out of room in the fpga (which is why i 
> suggested
> > it so that we could possibly get 90% of the performance of 10 rx's 
> with a
> > fraction of the fpga power used up)
> >
> > yes if there is enough fpga space and enough computer power then 
> multiple
> > rx's would be better
>
> This begs the question: How much FPGA space is currently used/free on
> Mercury and/or the other cards?
>
> ------------------------------------------------------------------------
>
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