[hpsdr] Ozy/Mercury Protocol

[John Melton]

This sounds familiar ;-)

It is exactly the problem I see with interfacing HPSDR with Jack on Linux.

-- John g0orx/n6lyt

On 08/18/09 11:35, Alberto I2PHD wrote:
> ***** High Performance Software Defined Radio Discussion List *****
> 
> 
> 
> ------------------------------------------------------------------------
> 
> Phil Harman wrote:
>> Dave is quite correct, given the bursty nature of PC processing we have
>> implemented large FIFOs in the FPGA code to account for this.
>>   
> Hi Phil and Dave,
> 
>   thanks for the answers. But there is still something that puzzles me.
> I am quite familiar with FIFO and Ring buffers, I use them extensively 
> both in Winrad
> and in the new code to interface the HPSDR HW.
> 
> But you need a timing to start a new signal processing cycle on the 
> PC... when data are coming
> from a sound card, that timing is given by the card interrupts, that 
> happen at a regular
> rate, given by the sampling frequency.
> 
> In the case of HPSDR, the only timing available is given by the arrival 
> of a new USB buffer,
> FIFO and Ring buffers can compensate for delays in obtaining CPU cycles 
> from the
> Windows scheduler, but cannot correct the timing.
> 
> And the inherent timing of the HPSDR HW is that of providing 63 samples. 
> Suppose you want
> to start a processing cycle that process a 512-sample buffer. How can 
> you obtain the right
> trigger to start it from the HPSDR timing ? 63 has no powers of two in 
> its prime decomposition,
> being it 3 * 3 * 7. So to have a timing without jitter you would need to 
> fill a buffer of 63 * 512 samples,
> and only when it is full you could start a processing cycle being 
> certain of having no jitter.
> 
> But that size is way too large, it would introduce unacceptable latency.
> If you do a close inspection at the process, you see that initially, to 
> fill a 512 sample buffer, you need
> 9 buffers of 63 samples, and you remain with (63 - 8) = 55 samples as 
> 'reservoir'.
> So for the second 512 sample buffer you need now only 8 buffers of 63 
> samples, using 8 samples
> taken from the 'reservoir'. And so on for some cycles. But then, when 
> the 'reservoir' is empty,
> you need again 9 buffers of 63 samples....
> 
> So the rate of preparation of the 512 sample buffers, which ultimately 
> is the rate that determines
> the timing of the signal processing cycle on the PC, is slightly uneven, 
> with some jitter. It alternates
> between 9 and 8 USB-interrupts (not the right word, but you understand 
> what I mean).
> And frankly I cannot understand how this jitter can be eliminated with 
> the use of FIFO and/or Ring buffers...
> 
> As said in my previous message, there are absolutely no consequences on 
> voice/music or CW
> signals. My fear is that those few data modes that require phase 
> coherence can be affected...
> 
> Sorry if I make you spending some time reading this...
> 
> 73  Alberto  I2PHD
> 
> 
>  
> 
> 
> ------------------------------------------------------------------------
> 
> _______________________________________________
> HPSDR Discussion List
> To post msg: hpsdr at openhpsdr.org
> Subscription help: http://lists.openhpsdr.org/listinfo.cgi/hpsdr-openhpsdr.org
> HPSDR web page: http://openhpsdr.org
> Archives: http://lists.openhpsdr.org/pipermail/hpsdr-openhpsdr.org/

 1250592452.0