[hpsdr] optimum Tx image rejection in DUC?

[Ken N9VV]

Hi, I am learning about the benefits of DDC for receive where 
there is no issue of "receiver image rejection" because it is 
always taken care of in an optimum mathematical manner in the FPGA.

Is the same thing true of a DUC transmitter? is Tx image rejection 
handled by the FPGA in a mathematically optimum manner?

Image rejection in the QSD type rigs has always been quite a 
challenge. In the DDC/DUC rigs, no one every mentions it. Does 
image rejection for both Rx and Tx just disappear in the FPGA?

tnx,
de Ken N9VV