[hpsdr] Disabling 10 MHz clock on Penelope

[Ray Anderson]

Alberto-

I believe the 122.8 MHz oscillator is a VCXO (actually a controllable
TCXO) and not a VCO. It seems to be rock-steady because it is a Xtal
oscillator.


-Ray  WB6TPU



> -----Original Message-----
> From: hpsdr-bounces at lists.openhpsdr.org [mailto:hpsdr-
> bounces at lists.openhpsdr.org] On Behalf Of Alberto I2PHD
> Sent: Monday, December 21, 2009 10:30 AM
> To: HPSDR (open)
> Subject: Re: [hpsdr] Disabling 10 MHz clock on Penelope
> 
> ***** High Performance Software Defined Radio Discussion List *****

Hi Dave,

  thanks for the explanation. I agree that it is not "High Performance"
but,of course I am not intending to use the HPSDR HW that way...
I was just curious to understand what was happening.
And I must say that those VCOs must be of an exceptional quality, as the
frequency is rock-stable- as if it were generated by a xtal.
That is what puzzled me.... had I noticed a warbling frequency, typical
of a free running oscillator, I had immediately understood
what was going on. There isn't the possibility that, somehow, due
perhaps to some stray coupling, the VCO does lock to one of the
reference clocks on one of the two boards ? It looks too stable for a
free running oscillator....

73  Alberto  I2PHD





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