[hpsdr] Verilog class

[Kirk Weedman]

I just want everyone to know we only have about 3 maybe 4 more classes 
left for this beginner/intermediate Verilog course - so hang in there.  
You actually know more than you think you do and hopefully things will 
start coming together in how to use all you've learned for both 
simulation and synthesis.  Once we're done and everyone is caught up, we 
can start digging into HPSDR Verilog RTL code.  In the next lecture, I'm 
thinking about beginning at 3:30 PM PST so I can show you more of the 
HPSDR code we were going through at the end of Lecture 7.  Then at 4PM 
we would start the lecture as usual.  Stay tuned...

Kirk KD7IRS

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