[hpsdr] Verilog class starting early today ???

[Michael Kreeger]

Graham,

Yes we are starting at 3:30 today to continue on the code walk through
we were doing on Monday.

Michael

On Thu, Feb 26, 2009 at 1:23 PM, Graham / KE9H <KE9H at austin.rr.com> wrote:
> ***** High Performance Software Defined Radio Discussion List *****
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>
>
> Kirk & Michael:
>
> Were you planning to start the class early today
>
> for the FPGA code content discussion?
>
> Thanks,
> --- Graham / KE9H
>
> ==
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-- 
Michael Kreeger
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