[hpsdr] Mercury: Selection of frequency Segments

[Alex, VE3NEA]

Hello,

I am working on a multi-receiver project based on the QS1R and Mercury
hardware. I managed to squeeze 7 independent receiver channels in the
Cyclone III EP3C25 FPGA - this was not an easy task, I had to rewrite all
modules from scratch to save logic elements. The Verilog part of the code is
finished and works fine on QS1R, the USB bandwidth is more than sufficient
for 7 receivers at 192 kHz, 2x32-bit. The 7-receiver source code is open
source, it is available on the QS1R SVN server. A number of modules from
this project are used in the Mercury V.2.x FPGA code.

Implementing multiple receivers in Mercury is more difficult than in QS1R,
the bottleneck is the serial protocol used to transfer I/Q data from Mercury
to Ozy. I don't think the 7-receiver code can be ported to Mercury until the
protocol is changed to 8-bit parallel. Any volunteers to do this?

The PC part of the project is work in progress, currently I only have the
code that receives seven I/Q data streams via USB - the CPU load is 2% to
12% on a dual-core 3-GHz P4, depending on the sampling rate and block size.

73 Alex VE3NEA





----- Original Message ----- 
From: "Steven Wilson" <stevew at intrinsix.com>
To: "Johan Maas" <johan.maas at hetnet.nl>; <hpsdr at lists.hpsdr.org>
Sent: Monday, January 05, 2009 12:30 PM
Subject: Re: [hpsdr] Mercury: Selection of frequency Segments


> ***** High Performance Software Defined Radio Discussion List *****
>
> Johan,
>
>>From my understanding of how Mercury works - you would have to modify
> the FPGA to pull this off.  There are several possible limits that may
> cause issues.
>
> The FPGA implements the DDC, i.e. you create I/Q by taking the raw data
> in from the A/D and multiply it by a phase angle changing at the
> frequency band you are listening too.  Consequently, to fit "two"
> receivers into the single FPGA you would first have to double the entire
> DDC structure within the FPGA.  The first limit you have to be concerned
> about is - will this second structure fit into the FPGA.
>
> The next limit is can the FPGA spit out a new multiplexed data stream
> containing both receiver's I/Q data to Ozy, is there enough bandwidth
> between the two to pull this off.
>
> Next is whether there is head-room in the USB communications from Ozy to
> your host computer.
>
> Finally - do you have enough Flops in your computer to process the
> second receiver.
>
> These are some of the limits I can see for an implementation with the
> current hardware.
>
> At the same time, I believe some people are using two Mercury's already
> - so maybe this is an existence proof of enough bandwidth in Ozy and
> USB.  (Two mercury's is the more expensive solution ;-)
>
> If anyone on the list wants to correct my statements above - then I'll
> learn something too!
>
> 73 de Steve KA6S
>
> Johan Maas wrote:
>> ***** High Performance Software Defined Radio Discussion List *****
>> 


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