[hpsdr] Call for Comments and Discussion - OzyII

[jeff millar]

Phil Harman wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> All,
>
> I've posted a preliminary block diagram of what OzyII could look like 
> on the Wiki -
>
> < http://openhpsdr.org/wiki/index.php?title=OZYII >
>
> It's basically a large, leaded, FPGA connected to a 10/100/1000 
> Ethernet PHY chip. The LVDS transceivers will provide high speed data 
> access to Mercury and other future projects to free us from any Atlas 
> bus limitations.
At a previous job we implemented an Ethernet layer 2 interface between a 
Linux processor and small Altera Cyclone FPGA that implemented a GSM 
cellular transciever. IIRC, the Ethernet framing took about 2000 logic 
elements in the FPGA. That approach works fine and Linux network drivers 
work fine without a Layer 3 wrapper on the packets. We had to change the 
network stack configuration to interrupt on every packet rather than 
waiting for 2 or more to accumulate to keep latency down. Linux had no 
problems keeping up with about 2500 small packets per second in each 
direction.

Vanu (SDR company) also uses Ethernet Layer 2 for connecting between 
many processors and the FPGA in many transcievers. The architecture 
gains scalability by routing all communcation through E-net switches.

With 2009 current technology, I'd suggest looking at PCI-express because 
it uses a memory R/W model rather than a packet model, supports plug and 
play configuration, and comes embedded as hard silicon in the new Arria 
line of FPGAs and have very scalable performance. This would require 
finding a way to export PCI-E from desktop and Laptop PC's.

If it's too soon for PCI-E for ham applications, Ethernet Layer 2 will 
do just fine. Stay away from a Layer 3 protocol, it doesn't serve any 
useful purpose.

People keep equating Ethernet with TCP/IP. NOT TRUE!!! Ethernet has 
layer 2 frames containing data addressed by MAC addresses. Layer 3 adds 
a lot of overhead, and features and uses IP addresses. For direct 
connected real time applications, stick to Layer 2 framing only.

I've worked on a couple of projects embedding processors into FPGA's, 
using Xilinx MIPS. Disappointing in each case. Hooking the processor 
into the rest of the FPGA ended up taking a lot of logic resources. The 
software tools did not provide much confidence. It just didn't seem like 
it was worth the trouble. Altera NIOS might be better. But, overall I 
think you have be highly motivated to want to put a processor in the FPGA.

I've also designed a system using USB for connecting to an SDR. ...also 
a somewhat disappointing experience. Achieving good performance required 
too many tricks. For Linux the trick are open, but for windows, there's 
a lot of secret sauce to make to work well.

There's little incentive to use Gig-Ethernet because if you try to pass 
that much data, the processor can't do anything with it. SDR algorithms 
probably can't use more than about 1 to 5Mbps of sample data Save the 
money and use a 10/100 Ethernet interface, it will last for a lot of PC 
technology evolution.

jeff, wa1hco
>
> 73's Phil...VK6APH

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