[hpsdr] Verilog Class

[Georg Prinz]

Hello Kirk,
thank you for your excellent lecture #10! 

Unfortuanately I couldn't find the testbench for OneWire_xmt/rcv. Would
you be so kind to point me straight to it?
Further more, I cannot open the file "ozyjanus_sim.vcd" with ModelSim.
It seems to be dump file.

Can you please explain in short the process how to proceed after
everything was simulated for a project in ModelSim. The compiled
project(which files?), can than be loaded straight into a FPLG or CPLD
via a Byteblaster?

After loading, the worst case wouldn't be unusual, that nothing will
happen. How to proceed?

Is it possible to reload OZYJANUS/MERCURY board directly without using a
Blaster, already? When yes, how?

Have a nice day
Georg, dl2kp


P.S.: I found following short introduction into Verilog on the Web. I
think it could be a good supplement to your lecture:
http://my.com.nthu.edu.tw/~jmwu/com5195/verilog.pdf





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