[hpsdr] Phoenix again
richardh at iinet.net.au
richardh at iinet.net.au
Wed Oct 28 04:50:12 PDT 2009
Dear all
Phoenix is not yet dead but I have reached a frustrating impasse
It seems that I cant solve the spur issues with the current board, though it does
work.
The spur amplitudes are quite "fixed" ie not affected by an "antenna" effect on
clock lines
They persist with the use of another clock source, so I dont think it is the DDS
Some clock signals are visible eg the 3.072 MHz clock and harmonics
I havent had the low noise 125MHz clock operational = it is probably better to do
this on a separate board if anyone wants it
I suspect that I have to go to a multilayer board and at the same time correct a
number of other issues
It would also be useful to get a firm set of software files ie
Ozy/Janus/PowerSDR/Phoenix object code as this has been a source of uncertainty
for me
The current errata file is as follows:
AD9912 PLL circuit = not completed
Need values for appropriate PLL multiplication
Need to establish whether there should be a bypass to gnd
at the power source to the PLL filter
If not remove C48
Regulators U5 U7 U8 U9
LK112S
Pin 1 SHDN should be tied to Vin Pin 5
Footprints wrong size
Inductors
Tranformers T1 2 4 5 6
extend pads out
Tantalums
QSE output amp
+ and - inputs wrong = reverse
U10
LT1117D33TR = this is SO8 package
Should be
LT1117S33TR SOT-223
BOM/Organizer
R70 is 1K
C101 10u ? correct
Looks like ceramic
C105 C106 Electros = wrong footprint
L25-28 FB ?not on BOM
R80 0R not on BOM
U12 LT1451 DAC 5V part = change to LTC1452
will run 3-5V
Janus uses phone size connector = switch to this from Ethernet style for Rx audio
out P4
But Janus connector does not have enough pins for balanced I/Q + GND
Unable to solve spur problem with current version of Phoenix
Probably need power/ground planes with multilayer board
Receiver input LPF to remove images
Change low noise Osc circuit to same source as Mercury 122MHz
Add various pads for testpoints
= DDS out to FPGA
= Mixer LO
= Audio out
Some questions
(1) I have no experience with multilayer boards = how many layers, and what on
each layer?
(2) Who makes prototypes at a reasonable cost?
(3) What issues should I look at when designing the layers?
(4) Any other design issues with Phoenix?
(5) Should I persist at all??
(I dont like to leave a project unfinished)
I would be grateful for views
Thanks
Richard VK6BRO
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