[hpsdr] CW with HPSDR

[Kirk Weedman]

I just looked at the schematic and Assignment Editor listing in 
Quartus.  Here's the scoop for what physically exists and what is in the 
Verilog.  See the Assignment Editor for the actual pinouts as the only 
the comments in Ozy_Janus.v for the DB9 pinouts are wrong. We can update 
the comments.

DB9 pin#     signal name in schematic  FPGA pin # in schematic    
function    GPIO_IN # in Quartus/Verilog
----------   ------------------------  -----------------------    
--------    ---------------------------------
6            FPGA_GPIO22               96                         
Dash        5
7            FPGA_GPIO23               97                         
Dot         6
8            FPGA_GPIO24               99                         
PTT         7

Thanks for posting
Kirk

Peter Uhrich wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> Hello all,
>
> due to an incorrect pin assignment in the verilog source file Ozy_Janus.v I
> have used DB9 pin 7 for dash and DB9 pin 8 for dot.
> Correct is DB9 pin 6 dash, DB9 pin 7 dot and DB9 pin 8 PTT.
>
> Phil VK6APH or Kirk KD7IRS be so kind and update this in Ozy_Janus.v
> Thank you in advance.
>
> 73 Peter DK7SP
>
>
>
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