[hpsdr] FIR Decimation...

[n3evl]

I was watching the 2008 presentation at the DCC made by Phil, VK6APH.  
There was some discussion in the final session on the DVD regarding 
whether or not the as-implemented FIR Decimation technique that involved 
elimination of multipliers was in fact valid.  I think the alternate 
approach discussed involved retaining all the multiplier stages and 
throwing away every other output sample.  I was wondering if anything 
further transpired and if the as-presented technique was either 
validated or perhaps replaced in the FPGA logic with the alternate method.

BTW, I really enjoyed watching the presentation - makes the operation of 
Mercury and the relationship between the FPGA code and the PC code much 
clearer - great job all round!

Pete, N3EVL