[hpsdr] PowerSDR v1.19.3.1.diversity9 (K5SO 5OCT2010)

[Phil Harman]

Hi Joe,

You should be able to do that with the existing code.  If you select the 
122.88MHz clock for both boards and in PowerSDR select

Hardware Config > Excalibur

then both boards should lock to a 10MHz clock from Excalibur (or a suitable 
10MHz clock on Atlas pin C16).

We did do a mod to the Mercury code some time ago to use a PLL to divide the 
10MHz rather than a counter - this gave much lower phase noise.  In which 
case you ran a wire from C16 on Mercury to the Aux Clock input (J8) from 
memory.

You may want to check the code to see which is currently being used to take 
the external clock input from C16 - either direct from that pin or via a PLL 
using J8.

73 Phil...VK6APH



----- Original Message ----- 
From: "Joe Martin K5SO" <k5so at valornet.com>
To: <hpsdr at lists.openhpsdr.org>
Sent: Wednesday, October 06, 2010 8:48 AM
Subject: Re: [hpsdr] PowerSDR v1.19.3.1.diversity9 (K5SO 5OCT2010)


> ***** High Performance Software Defined Radio Discussion List *****
>
> Phil,
>
> That's a great idea, of course; to lock both 122.88MHz oscillators to
> the Excalibur 10MHz signal on the Atlas bus.  I'd love to do that!
>
> Trouble is I need a bit of guidance as to how to actually get it done,
> hihi.  I'll sure put the time in on the Verilog code if you can get me
> headed in the right direction with a game plan for the code.
>
> 73,  Joe K5SO
>
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