[hpsdr] Fwd: Re: Pennylane drivelevel

[wully]

Hi Phil

Now I have verified, that the IQ-Signal is available at Pins 16 and 3 of 
the DB25. The value I read for full power at Penny is 3Vpp for a twotone 
test signal. No power output at DriveLevel 255
I am stuck.

73, Alfred

-------- Original Message --------
Subject: 	Re: [hpsdr] Pennylane drivelevel
Date: 	Fri, 01 Jul 2011 09:38:49 +0200
From: 	wully <wully at bluewin.ch>
To: 	phil at pharman.org



Hi Phil

Thank you for the confirm of my analysis. On penelope, my code works ok
for many month now, but pennylane does not yet produce output, even
setting 255 in DriveLevel. I am reading the AD-Value AIN5, on penny this
shows above 3000 when at full power, on pennylane it stays allways at
95-96 (no output). But my code has not changed with respect to
IQ-Generation. The microphone circuit works ok on PL, since I see the
samples from the mic in my program.
Setting PTT induces fast blinking of LED7 as it should. So, I don't yet
understand.

  I will analyze the Pins 16 and 3 of DB25, to see the IQ-Signals.
73
Alfred

On 01.07.2011 03:15, Phil Harman wrote:
>  Hi Wully,
>
>  You appear to be on the right track. The Drive Level can vary from 0x00
>  (no power out) to 0xFF (max power out).
>
>  You only really need to set this each time the drive level is changed
>  since once set it will be saved in an FPGA register. However, most PC code
>  continually sends all the C&C bytes in round-robin fashion to cater for
>  dropped packets on the USB link.
>
>  Unlike Penny, for PennyLane the I and Q signals need to be held at full
>  scale at all times - we usually use AGC to do this.
>
>  You can monitor the level of your Q signal from the PC by connecting a
>  'scope to the output of the TLV320 on the DB25 connector. In this way you
>  can check that PennyLane is actually receiving your I and Q signals.
>
>  Hope that helps.
>
>  73 Phil...VK6APH
>

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