[hpsdr] SunSDR2 - new TRX

[Phil Harman]

Hi Alex,

Thanks for your comments and interest in Hermes.

I've just done a compile of a single receiver version of Hermes that 
includes full support for  Ethernet, transmitter, Alex and Apollo and 10MHz 
reference input.  This uses  60% of the EP3C40.  In which case, based on 
your previous work, it should be possible to include 7 receivers in Hermes.

>From memory I think you use interpolation of the receive frequency in the 
PC, rather than finer CORDIC steps, in order to reduce the FPGA footprint of 
each receiver.

There are no bottlenecks in the hardware that will prevent this and we have 
full  Gigabit Ethernet to the PC available.

73 Phil...VK6APH



-----Original Message----- 
From: Alex VE3NEA
Sent: Monday, June 04, 2012 3:43 AM
To: HPSDR list
Subject: Re: [hpsdr] SunSDR2 - new TRX

***** High Performance Software Defined Radio Discussion List *****

Joe,

My 7-channel FPGA code is released under the GPL license and is available at
several places on the Internet, including the HPSDR SVN server:

(http://svn.tapr.org/repos_sdr_hpsdr/trunk/VE3NEA/7_channel_Verilog/)

Feel free to use this code in your work.

I am really hoping that Hermes is capable of receiving on all Ham bands
simultaneously. Please let me know if there are any bottlenecks in the 
hardware
that make this impossible.

73 Alex VE3NEA




-----Original Message----- 
From: Joe Martin K5SO
Sent: Sunday, June 03, 2012 3:19 PM
To: HPSDR list
Subject: Re: [hpsdr] SunSDR2 - new TRX

***** High Performance Software Defined Radio Discussion List *****

Hi Alex,

The 4 Rx implementation we use simply copies the code for a single Rx into 
other
locations for the multiple receivers, so size required scales linearly with 
the
number of receivers implemented.  If that approach is taken, no more than 
four
such units will fit in the FPGA (with all the Tx and other code that is 
present
in Hermes).

Without knowing specifically how you implement your 7 receivers I really 
can't
comment definitively on the differences.  I imagine that you can comment on 
that
better than I.  Is it possible that in your QS1R code you use less 
decimation in
the FPGA (resulting in a coarser step resolution) and then perhaps later 
apply
more processing/decimation to the stream on the PC side?  Or is the 
additional
overhead of ethernet, transmit, and other features inherent in the Hermes 
FPGA
taking up the additional space that the Rx-only QS1R doesn't have to worry 
with?

73,  Joe K5SO

On Jun 3, 2012, at 12:32 PM, Alex VE3NEA wrote:

> ***** High Performance Software Defined Radio Discussion List *****
>
> Hi Joe,
>
> I am very surprised that only 2 or 3 receivers is the realistic loading of 
> Hermes. I have 7 receivers implemented in the EP3C25 FPGA of QS1R, and I 
> was hoping that Hermes, with its EP3C40 chip, would allow even more 
> receivers. What is the bottleneck?
>
> 73 Alex VE3NEA
>
>

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